Programmer notes: Xilinx

Friday, January 20, 2012

Connect clock signal to FPGA output pad

So now i know how to connect some internal clock signal to the output pin. Direct connection is impossible because the only dedicated clock signal buses can be connected only to the clock input pins of the internal flip-flops.
The internal clock signal can be connected to the output pin or to non clock signal with the following construct:

Here is the VHDL sample:

oddr2_0 : ODDR2
    port map(
        Q           => Output_clk_o,
        C0          => Output_clk_i,
        C1          => Output_clk_i,
        D0          => '0',
        D1          => '1'
    );

obuf_0 : OBUF
    generic map (
        CAPACITANCE => "NORMAL",
        IOSTANDARD  => "LVCMOS33",
        SLEW        => "FAST"
    )
    port map (
        O => Output_clk,
        I => Output_clk_o
    );

Where

Output_clk_i is some internal input clock signal
Output_clk_o is intermediate wire between ODDR2 and OBUF
Output_clk is output clock signal, which can be connected to the non clock input or to the output pin.

Same can be made for differential output clock:

Here is the VHDL sample:

oddr2_0 : ODDR2
    port map(
        Q           => Output_clk_o,
        C0          => Output_clk_i,
        C1          => Output_clk_i,
        D0          => '0',
        D1          => '1'
    );

obuf_0 : OBUFDS
    generic map (
        CAPACITANCE => "NORMAL",
        IOSTANDARD  => "LVDS_33",
        SLEW        => "FAST"
    )
    port map (
        O => Output_clk,
        OB => Output_clk_n,
        I => Output_clk_o
    );

Where

Output_clk_i is some internal input clock signal
Output_clk_o is intermediate wire between ODDR2 and OBUF
Output_clk is output clock signal, which can be connected to the non clock input or to the output pin.
Output_clk_n is negative output clock signal, which can be connected to the non clock input or to the output pin.

In the VHDL file in entity block you must define this signals as clock for simulation:

attribute SIGIS : string;
attribute SIGIS of Output_clk         : signal is "CLK";
attribute SIGIS of Output_clk_n       : signal is "CLK";

If you use this code for embedded Xilinx MicroBlaze you must define this signal in MPD file as follow:

PORT Output_clk      = "", DIR = O, SIGIS = CLK
PORT Output_clk_n      = "", DIR = O, SIGIS = CLK

This information is get from Spartan-6 FPGA Clocking Resources on page 112.

Programmer notes

Friday, January 20, 2012

Connect clock signal to FPGA output pad

Sunday, January 15, 2012

Usefull user constraints for axi_ethernet