Showing posts with label axi_ethernet. Show all posts
Showing posts with label axi_ethernet. Show all posts

Sunday, January 15, 2012

Usefull user constraints for axi_ethernet

If you try to get hardware design using axi_ethernet core you may to need this recommended constraints:
AXI_Ethernet v3.00.a - Recommended Constraints for AXI-based Ethernet Systems

The above link doesn't exists any more :( Here is carbon copy of them:

This Answer Record provides links to zip files with the recommended constraints for the AXI_Ethernet v3.00.a core logic. The constraints for the Ethernet pins themselves are not included. These constraints have been tested on specific development boards and some attributes such as IDELAY, IDELAYCTRL, and GTP/GTX locations can change in custom implementations.

Designs with AVB Endpoint Enabled (C_AVB = 1)

Virtex-6 Hard TEMAC Implementations 

Virtex-6 Soft TEMAC Implementations 

Spartan-6 Soft TEMAC Implementations 

Designs without AVB Endpoint Enabled (C_AVB = 0)

Virtex-6 Hard TEMAC Implementations 

Virtex-6 Soft TEMAC Implementations 

Spartan-6 Soft TEMAC Implementations