Now I describe short what you need, if EDK say you that it can't find site for some PLL in clock generator you create in design. You must write in the constraint file (usually data\system.ucf) following code:
INST "clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y1";
The appropriate site you can find in the Spartan-6 FPGA Clocking Resources on the page 93 in table 3-1:
Table 3-1: PLLs with Direct Connections to BUFPLL
BUFPLL Location | Bank | Valid PLL Locations by Device Type | ||
LX4, LX9, LX16, LX25/LX25T | LX45/LX45T | LX75/LX75T LX100/LX100T LX150/LX150T | ||
BUFPLL_X1Y5 BUFPLL_X1Y4 BUFPLL_MCB_X1Y9 | 0 | PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0 |
BUFPLL_X2Y2 BUFPLL_X2Y3 BUFPLL_MCB_X2Y5 | 1 (5) | PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0 |
BUFPLL_X1Y0 BUFPLL_X1Y1 BUFPLL_MCB_X1Y5 | 2 | PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0 |
BUFPLL_X0Y2 BUFPLL_X0Y3 BUFPLL_MCB_X0Y5 | 3 (4) | PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0 | PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0 |