So now i know how to connect some internal clock signal to the output pin. Direct connection is impossible because the only dedicated clock signal buses can be connected only to the clock input pins of the internal flip-flops.
The internal clock signal can be connected to the output pin or to non clock signal with the following construct:
Here is the VHDL sample:
The internal clock signal can be connected to the output pin or to non clock signal with the following construct:
oddr2_0 : ODDR2
port map(
Q => Output_clk_o,
C0 => Output_clk_i,
C1 => Output_clk_i,
D0 => '0',
D1 => '1'
);
obuf_0 : OBUF
generic map (
CAPACITANCE => "NORMAL",
IOSTANDARD => "LVCMOS33",
SLEW => "FAST"
)
port map (
O => Output_clk,
I => Output_clk_o
);
Where
Here is the VHDL sample:
Output_clk_iis some internal input clock signalOutput_clk_ois intermediate wire between ODDR2 and OBUFOutput_clkis output clock signal, which can be connected to the non clock input or to the output pin.
Same can be made for differential output clock:
oddr2_0 : ODDR2
port map(
Q => Output_clk_o,
C0 => Output_clk_i,
C1 => Output_clk_i,
D0 => '0',
D1 => '1'
);
obuf_0 : OBUFDS
generic map (
CAPACITANCE => "NORMAL",
IOSTANDARD => "LVDS_33",
SLEW => "FAST"
)
port map (
O => Output_clk,
OB => Output_clk_n,
I => Output_clk_o
);
Where
In the VHDL file in entity block you must define this signals as clock for simulation:Output_clk_iis some internal input clock signalOutput_clk_ois intermediate wire between ODDR2 and OBUFOutput_clkis output clock signal, which can be connected to the non clock input or to the output pin.Output_clk_nis negative output clock signal, which can be connected to the non clock input or to the output pin.
attribute SIGIS : string;
attribute SIGIS of Output_clk : signal is "CLK";
attribute SIGIS of Output_clk_n : signal is "CLK";
PORT Output_clk = "", DIR = O, SIGIS = CLK
PORT Output_clk_n = "", DIR = O, SIGIS = CLK
